(a) Field of the Invention
The present invention relates to a plasma display panel (“PDP”) and a driving method thereof, and more particularly to an energy recovery circuit and a method for driving the same that directly contribute to plasma display discharge.
(b) Description of the Related Art
In recent years, flat panel displays such as liquid crystal displays (LCD), field emission displays (FED), PDPs, and the like have been actively developed. The PDP has advantages over the other flat panel displays because of its high luminance, high luminous efficiency, and wide view angle. Accordingly, the PDP is a preferred large-scale screen of larger than 40 inches that can substitute for the conventional display.
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. It includes, depending on its size, more than several dozens to millions of pixels arranged in a matrix pattern. Such a PDP is classified as a direct current (DC) type or an alternating current (AC) type according to its discharge cell structure and the waveform of the driving voltage applied thereto.
The DC type PDP has electrodes exposed to a discharge space to allow DC to flow through the discharge space while the voltage is applied, and thus requires a resistance for limiting the current. To the contrary, the AC type PDP has electrodes covered with a dielectric layer that forms a capacitor to limit the current and protect the electrodes from the impact of ions during discharge. Thus, the AC type PDP has a longer lifetime than the DC type PDP.
Typically, the driving method of the AC type PDP is composed of a reset step, an addressing step, a sustain step, and an erase step.
In the reset step, the state of each cell is initialized to be ready for addressing the cell. In the addressing step, wall charges are applied in a selected cell that is on the panel (i.e., addressed cell). In the sustain step, a discharge occurs to actually display an image on the addressed cells. In the erase step, the wall charges on the cells are erased to finish the sustained discharge.
In the AC type PDP, the address electrodes for addressing act as a capacitive load, so that there is a capacitance for the electrodes and a need for a reactive power as well as a power for the addressing in order to apply waveforms for addressing. A circuit for recovering the reactive power and reusing it is called an energy recovery circuit.
A conventional energy recovery circuit for the AC type PDP and its driving method are now described.
FIGS. 1 and 2 show a conventional energy recovery circuit and its waveform diagram, respectively.
FIG. 1 shows the energy recovery circuit disclosed in the U.S. Pat. Nos. 4,866,349 and 5,081,400 issued to L. F. Weber.
The conventional energy recovery circuit includes two serially connected switching elements S1 and S2, diodes D1 and D2, inductor LC and energy recovery capacitor CC, and two serially connected switches S3 and S4.
A contact between the two switching elements S3 and S4 is coupled to the PDP, which is represented by a capacitor CP in an equivalent circuit.
The conventional energy recovery circuit as constructed above operates in four modes according to the states of the switching elements S1 to S2, and shows the waveforms of output voltage VP and current IL flowing to inductor LC, as illustrated in FIG. 2.
Switching element S4 is initially turned on right before switch S1 is turned on, so that terminal voltage VP of the panel is at zero. In the meantime, energy recovery capacitor CC is already charged with a voltage (Va/2) that is half address voltage Va.
At t0, while terminal voltage VP of the panel is maintained at zero, mode 1 begins to turn switching element S1 on and switching elements S2, S3, and S4 off.
In the operational interval (t0 to t1) of mode 1, an LC resonance path is formed involving energy recovery capacitor CC, switching element S1, diode D1, inductor Lc, and plasma panel capacitor CP. Accordingly, current IL flowing through inductor LC forms a half waveform because of LC resonance, and output voltage VP of the panel gradually increases to address voltage VS. At the moment that output voltage VP of the panel reaches address voltage VS, almost no current flows to inductor Lc.
The mode 2 begins at the end of mode 1, to turn switching elements S1 and S3 on and switches S2 and S4 off. In the operational interval (t1 to t2) of mode 2, externally supplying voltage Va is applied to panel capacitor CP via switching element S3 to maintain output voltage VP of the panel.
Once mode 2 ends in the state of maintaining discharge of terminal voltage VP, mode 3 begins to turn switch S2 on and switches S1, S3,and S4 off.
In the operational interval (t2 to t3) of mode 3, an LC resonance path is formed in reverse path of the LC resonance path in mode 1, i.e., a current path including plasma panel capacitor CP, inductor Lc, diode D2, switching element S2, and energy recovery capacitor CC in sequence. Accordingly, as shown in FIG. 2, current IL flows to inductor Lc and output voltage VP of the panel falls, so that current IL of inductor LC and output voltage VP of the panel reach zero at t3.
In the operational interval of mode 4, switches S2 and S4 are turned on and switching elements S1 and S3 are turned off to maintain output voltage VPof the panel at zero. Once switching element S1 is turned on in this state, the cycle returns to mode 1.
In the conventional energy recovery circuit configured as above, however, there is a problem that all of the energy is not recovered due to loss of the circuit itself such as ON loss of the switching elements or the switching loss. Thereby, the address voltage cannot be increased to a desired voltage Va or cannot be decreased to a ground voltage, and this causes a hard-switching of the switching elements. In addition, a rising time and a falling time of the address voltage become longer, and this causes the addressing speed to be lower.